The invention relates to an integrated circuit comprising processing device, such as a micro controller or micro processor.
Digital signal processors (DSP), such as those in modem chips, commonly include a program interface and a data interface. The program interface comprises an address bus and a data bus and the data interface also comprises another address bus and another data bus. Each of the four buses will normally have 16 parallel lines. Hence, if each of the four buses is required to connect to a memory, or other device, outside of the integrated circuit in which the DSP is located, a pin for each line on each bus is required. Typically, three pins are also required for control signals. Hence, the total number of pins required on the integrated circuit to communicate with the DSP is 70 pins. As a large element of the cost of producing integrated circuits is dependent on the number of pins required by the integrated circuit to communicate with external devices, the provision of 70 pins results in an expensive integrated circuit.
One method of reducing the number of external pins is to locate more memory devices on the integrated circuit itself to reduce the requirement of the DSP to communicate with external devices. However, memory tends to be expensive and to incorporate large memory capacities onto an integrated circuit is expensive. There is also the disadvantage that the memory cannot be upgraded without replacing the entire integrated circuit, including the DSP and other components which may not require to be upgraded.
Therefore, it is desirable to locate the memories outside of the integrated circuit on which the DSP is located to permit memories to be easily upgraded.
A solution to reduce the number of pins for communicating with the program interface and data interface of the DSP, while maintaining memory devices outside the integrated circuit, is to couple the data and program address buses to an internal switching device within the integrated circuit which can couple either of the address buses to an external address bus and similarly couple the data buses to another switching device which permits either one of the data buses to be coupled to an external data bus.
Although this solution reduces the number of pins on the integrated circuit, it has the disadvantage that it requires firm ware on the integrated circuit to control the switching devices. In addition, the switching devices can only be switched when the buses are not in use and furthermore, a number of clock cycles are required to perform the switching operation. Hence, for example, if the buses for the program interface are coupled to the external address and data buses, the switching devices can only switch the data interface buses to the external address and data buses after the program interface has finished using the external address and data buses. After the program interface has finished using the external address and data buses, a number of clock cycles are required before the data interface can commence use of the external address and data buses.
Therefore, although the cost of the packaging is reduced for the integrated circuit by reducing the number of pins, the speed at which the DSP can access the external memories is limited by the switching time, and that only the program interface or the data interface can be coupled to the external address and data buses at any one time.
In accordance with the present invention, an integrated circuit comprises a processing device; a program interface coupled to the processing device, the program interface comprising a first address bus and a first data bus; a data interface coupled to the processing device, the data interface comprising a second address bus and a second data bus; an address bus switching device adapted be coupled to an external address bus, the address bus switching device coupled to the first and second address buses; a data bus switching device adapted to be coupled to an external data bus, the data bus switching device coupled to the first and second data buses; and a control device coupled to the processing device, the address bus switching device and the data bus switching device, the control device controlling the address and data bus switching devices to couple the first address bus and the first data bus to the external address and data buses or to couple the second address bus and the second data bus to the external address and data buses, in response to control signals received from the processing device.
An advantage of the invention is that by providing an integrated circuit with a processing device and a control device coupled to the processing device and to the data and address bus interfaces, it is possible to switch the external data and address buses between the program interface and the data interface during the same clock cycle.
Preferably, the control device comprises arbitration means which prioritises requests for coupling to the external address and data buses from the program interface and the data interface. Typically, the arbitration means allocates priority to the program interface.
Preferably, the control device further comprises a delay generation means which generates a delay signal which the control device sends to the processing device to prolong a processing device cycle to correspond to an access speed of an external memory being accessed by the processing device through the data and address bus switching devices.
Preferably, the delay generation means generates delays which are a multiple of the processing device fundamental clock cycle period.
An example of an integrated circuit in accordance with the invention will now be described with reference to the accompanying drawings, in which:
FIG. 1 is a schematic view of an integrated circuit having a digital signal processor and incorporating a common bus interface unit;
FIG. 2 is a schematic diagram showing a simplified architecture of the common bus interface unit;
FIG. 3 is a state table for the common bus interface unit shown in FIG. 2;
FIG. 4 shows a first state diagram for the common bus interface unit;
FIG. 5 shows a second state diagram for the common bus interface unit;
FIG. 6 shows a third state diagram for the common bus interface unit; and
FIG. 7 shows a schedule of events for a program read and data write operation for the integrated circuit shown in FIG. 1.